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<!@TC:1538962897>
#Build: Synplify Pro (R) N-2018.03G-Beta6, Build 118R, May 15 2018
#install: C:\Gowin\1.8\SynplifyPro
#OS: Windows 8 6.2
#Hostname: BEACONDEV3

# Mon Oct  8 09:41:37 2018

#Implementation: rev_1


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=compilerReport1></a>Synopsys HDL Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1538962899> | Running in 64-bit mode 

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=compilerReport2></a>Synopsys Verilog Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1538962899> | Running in 64-bit mode 
@N: : <!@TM:1538962899> | : Running Verilog Compiler in System Verilog mode 
@N: : <!@TM:1538962899> | : Running Verilog Compiler in Multiple File Compilation Unit mode 
@I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Gowin\gowin-blink\impl\temp\gao\ao_0\gw_ao_parameter.v" (library work)
@I::"C:\Gowin\gowin-blink\impl\temp\gao\ao_0\gw_ao_top_define.v" (library work)
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_define.v" (library work)
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_mem_ctrl.v" (library work)
<font color=#A52A2A>@W:<a href="@W:CG1337:@XP_HELP">CG1337</a> : <a href="C:\Gowin\1.8\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_mem_ctrl.v:104:9:104:28:@W:CG1337:@XP_MSG">gw_ao_mem_ctrl.v(104)</a><!@TM:1538962899> | Net capture_length_zero is not declared.</font>
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_top.v" (library work)
Verilog syntax check successful!
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Gowin\gowin-blink\impl\temp\gao\ao_0\gw_ao_parameter.v:1:0:1:9:@N:CG364:@XP_MSG">gw_ao_parameter.v(1)</a><!@TM:1538962899> | Synthesizing module work_C:\Gowin\gowin-blink\impl\temp\gao\ao_0\gw_ao_parameter.v_unit in library work.
Selecting top level module ao_top
Extracted state machine for register module_state
State machine has 6 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 76MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Oct  8 09:41:38 2018

###########################################################]

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=compilerReport3></a>Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1538962899> | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Oct  8 09:41:39 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Oct  8 09:41:39 2018

###########################################################]

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<!@TC:1538962897>

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Database state : C:\Gowin\gowin-blink\impl\temp\gao\ao_0\rev_1\synwork\|rev_1
<a name=compilerReport4></a>Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1538962901> | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Oct  8 09:41:40 2018

###########################################################]

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<!@TC:1538962897>
Premap Report


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<!@TC:1538962897>
# Mon Oct  8 09:41:41 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=mapperReport5></a>Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1086R, Built May 17 2018 10:22:59</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1538962904> | No constraint file specified. 
Linked File:  <a href="C:\Gowin\gowin-blink\impl\temp\gao\ao_0\rev_1\ao_0_scck.rpt:@XP_FILE">ao_0_scck.rpt</a>
Printing clock  summary report in "C:\Gowin\gowin-blink\impl\temp\gao\ao_0\rev_1\ao_0_scck.rpt" file 
@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1538962904> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1538962904> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1538962904> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

@N:<a href="@N:BN133:@XP_HELP">BN133</a> : <!@TM:1538962904> | Ignoring syn_hier=hard property on top-level design. 

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

@N:<a href="@N:MH105:@XP_HELP">MH105</a> : <!@TM:1538962904> | UMR3 is only supported for HAPS-80. 
@N:<a href="@N:MH105:@XP_HELP">MH105</a> : <!@TM:1538962904> | UMR3 is only supported for HAPS-80. 
Encoding state machine module_state[5:0] (in view: work.ao_top(verilog))
original code -> new code
   0000 -> 000001
   0001 -> 000010
   0010 -> 000100
   0011 -> 001000
   0100 -> 010000
   0101 -> 100000
syn_allowed_resources : blockrams=10  set on top level netlist ao_top

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)



<a name=mapperReport6></a>Clock Summary</a>
******************

          Start                 Requested     Requested     Clock        Clock                     Clock
Level     Clock                 Frequency     Period        Type         Group                     Load 
--------------------------------------------------------------------------------------------------------
0 -       ao_top|control[0]     164.5 MHz     6.078         inferred     Autoconstr_clkgroup_1     103  
                                                                                                        
0 -       ao_top|clk_i          240.4 MHz     4.160         inferred     Autoconstr_clkgroup_0     27   
========================================================================================================



Clock Load Summary
***********************

                      Clock     Source               Clock Pin                 Non-clock Pin     Non-clock Pin       
Clock                 Load      Pin                  Seq Example               Seq Example       Comb Example        
---------------------------------------------------------------------------------------------------------------------
ao_top|control[0]     103       control[0](port)     data_register[25:0].C     -                 -                   
                                                                                                                     
ao_top|clk_i          27        clk_i(port)          rst_ao.C                  -                 clk_ao.I[0](keepbuf)
=====================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



<a name=clockReport7></a>#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[</a>

2 non-gated/non-generated clock tree(s) driving 126 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

============================= Non-Gated/Non-Generated Clocks =============================
Clock Tree ID     Driving Element     Drive Element Type        Fanout     Sample Instance
------------------------------------------------------------------------------------------
<a href="@|L:C:\Gowin\gowin-blink\impl\temp\gao\ao_0\rev_1\synwork\ao_0_prem.srm@|S:ENCRYPTED@|E:ENCRYPTED@|F:@syn_dgcc_clockid0_0==1@|M:ClockId_0_0 @XP_NAMES_BY_PROP">ClockId_0_0</a>       ENCRYPTED           Unconstrained_port        23         ENCRYPTED      
<a href="@|L:C:\Gowin\gowin-blink\impl\temp\gao\ao_0\rev_1\synwork\ao_0_prem.srm@|S:ENCRYPTED@|E:ENCRYPTED@|F:@syn_dgcc_clockid0_1==1@|M:ClockId_0_1 @XP_NAMES_BY_PROP">ClockId_0_1</a>       ENCRYPTED           Unconstrained_io_port     103        ENCRYPTED      
==========================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: : <!@TM:1538962904> | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1538962904> | Writing default property annotation file C:\Gowin\gowin-blink\impl\temp\gao\ao_0\rev_1\ao_0.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 190MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 190MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 104MB peak: 190MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Mon Oct  8 09:41:43 2018

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<!@TC:1538962897>
Map & Optimize Report


</pre></samp></body></html>
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<!@TC:1538962897>
# Mon Oct  8 09:41:44 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=mapperReport8></a>Synopsys Generic Technology Mapper, Version mapgw, Build 1086R, Built May 17 2018 10:22:59</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1538962910> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1538962910> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1538962910> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Available hyper_sources - for debug and ip models
	None Found

@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1538962910> | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 194MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -3.10ns		 154 /       114
   2		0h:00m:01s		    -3.10ns		 153 /       114
   3		0h:00m:01s		    -3.12ns		 154 /       114
   4		0h:00m:01s		    -2.95ns		 154 /       114
   5		0h:00m:01s		    -3.12ns		 154 /       114
   6		0h:00m:01s		    -2.95ns		 154 /       114
   7		0h:00m:01s		    -3.12ns		 154 /       114
   8		0h:00m:01s		    -2.95ns		 154 /       114

   9		0h:00m:02s		    -2.95ns		 158 /       114
  10		0h:00m:02s		    -2.95ns		 159 /       114
  11		0h:00m:02s		    -2.95ns		 159 /       114
  12		0h:00m:02s		    -2.95ns		 159 /       114
  13		0h:00m:02s		    -2.95ns		 159 /       114


  14		0h:00m:02s		    -2.92ns		 156 /       114
  15		0h:00m:02s		    -3.09ns		 157 /       114
  16		0h:00m:02s		    -2.84ns		 157 /       114
  17		0h:00m:02s		    -2.84ns		 157 /       114
  18		0h:00m:02s		    -2.84ns		 157 /       114
  19		0h:00m:02s		    -2.84ns		 157 /       114
  20		0h:00m:02s		    -2.84ns		 157 /       114

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 194MB peak: 195MB)

@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1538962910> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 194MB peak: 195MB)


Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 123MB peak: 195MB)

Writing Analyst data base C:\Gowin\gowin-blink\impl\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 192MB peak: 195MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 193MB peak: 195MB)

@N:<a href="@N:BW103:@XP_HELP">BW103</a> : <!@TM:1538962910> | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:<a href="@N:BW107:@XP_HELP">BW107</a> : <!@TM:1538962910> | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 192MB peak: 195MB)


Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 193MB peak: 195MB)

<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1538962910> | Found inferred clock ao_top|clk_i with period 6.20ns. Please declare a user-defined clock on port clk_i.</font> 
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1538962910> | Found inferred clock ao_top|control[0] with period 8.47ns. Please declare a user-defined clock on port control[0].</font> 


<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
<a name=pnr10></a># Timing Report written on Mon Oct  8 09:41:49 2018</a>
#


Top view:               ao_top
Requested Frequency:    118.1 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1538962910> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1538962910> | Clock constraints include only register-to-register paths associated with each individual clock. 



<a name=performanceSummary11></a>Performance Summary</a>
*******************


Worst slack in design: -1.494

                      Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock        Frequency     Frequency     Period        Period        Slack      Type         Group                
---------------------------------------------------------------------------------------------------------------------------
ao_top|clk_i          161.2 MHz     137.1 MHz     6.202         7.297         -1.095     inferred     Autoconstr_clkgroup_0
ao_top|control[0]     118.1 MHz     100.4 MHz     8.465         9.959         -1.494     inferred     Autoconstr_clkgroup_1
System                100.0 MHz     167.1 MHz     10.000        5.984         4.016      system       system_clkgroup      
===========================================================================================================================





<a name=clockRelationships12></a>Clock Relationships</a>
*******************

Clocks                                |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------------------
Starting           Ending             |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------------------
System             ao_top|clk_i       |  6.202       4.016   |  No paths    -      |  No paths    -      |  No paths    -    
System             ao_top|control[0]  |  8.465       5.214   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top|clk_i       System             |  6.202       4.814   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top|clk_i       ao_top|clk_i       |  6.202       -1.095  |  6.202       4.681  |  No paths    -      |  3.101       1.580
ao_top|clk_i       ao_top|control[0]  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top|control[0]  System             |  8.465       6.894   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top|control[0]  ao_top|clk_i       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top|control[0]  ao_top|control[0]  |  8.465       -1.494  |  No paths    -      |  No paths    -      |  No paths    -    
=============================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo13></a>Interface Information </a>
*********************

No IO constraint found



====================================
<a name=clockReport14></a>Detailed Report for Clock: ao_top|clk_i</a>
====================================



<a name=startingSlack15></a>Starting Points with Worst Slack</a>
********************************

                                      Starting                                                         Arrival           
Instance                              Reference        Type      Pin     Net                           Time        Slack 
                                      Clock                                                                              
-------------------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_addr[6]     ao_top|clk_i     DFFCE     Q       capture_mem_addr[6]           0.367       -1.095
u_ao_mem_ctrl.capture_mem_addr[3]     ao_top|clk_i     DFFCE     Q       capture_mem_addr[3]           0.367       -1.027
u_ao_mem_ctrl.capture_mem_addr[7]     ao_top|clk_i     DFFCE     Q       capture_mem_addr[7]           0.367       -0.818
internal_reg_start_dly[0]             ao_top|clk_i     DFFC      Q       internal_reg_start_dly[0]     0.367       -0.775
capture_start_sel                     ao_top|clk_i     DFFCE     Q       capture_start_sel             0.367       -0.708
internal_reg_start_dly[1]             ao_top|clk_i     DFFC      Q       internal_reg_start_dly[1]     0.367       -0.559
u_ao_mem_ctrl.capture_mem_addr[4]     ao_top|clk_i     DFFCE     Q       capture_mem_addr[4]           0.367       0.297 
u_ao_mem_ctrl.capture_mem_addr[2]     ao_top|clk_i     DFFCE     Q       capture_mem_addr[2]           0.367       0.364 
u_ao_mem_ctrl.capture_mem_addr[5]     ao_top|clk_i     DFFCE     Q       capture_mem_addr[5]           0.367       0.574 
u_ao_mem_ctrl.capture_mem_addr[1]     ao_top|clk_i     DFFCE     Q       capture_mem_addr[1]           0.367       0.703 
=========================================================================================================================


<a name=endingSlack16></a>Ending Points with Worst Slack</a>
******************************

                                      Starting                                                      Required           
Instance                              Reference        Type      Pin     Net                        Time         Slack 
                                      Clock                                                                            
-----------------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr          ao_top|clk_i     DFFCE     CE      un1_start_reg_0_mb_mb      6.069        -1.095
u_ao_mem_ctrl.capture_mem_addr[0]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[0]     6.069        0.076 
u_ao_mem_ctrl.capture_mem_addr[1]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[1]     6.069        0.076 
u_ao_mem_ctrl.capture_mem_addr[2]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[2]     6.069        0.076 
u_ao_mem_ctrl.capture_mem_addr[3]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[3]     6.069        0.076 
u_ao_mem_ctrl.capture_mem_addr[4]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[4]     6.069        0.076 
u_ao_mem_ctrl.capture_mem_addr[5]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[5]     6.069        0.076 
u_ao_mem_ctrl.capture_mem_addr[6]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[6]     6.069        0.076 
u_ao_mem_ctrl.capture_mem_addr[7]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[7]     6.069        0.076 
u_ao_mem_ctrl.capture_mem_addr[8]     ao_top|clk_i     DFFCE     D       capture_mem_addr_lm[8]     6.069        0.076 
=======================================================================================================================



<a name=worstPaths17></a>Worst Path Information</a>
<a href="C:\Gowin\gowin-blink\impl\temp\gao\ao_0\rev_1\ao_0.srr:srsfC:\Gowin\gowin-blink\impl\temp\gao\ao_0\rev_1\ao_0.srs:fp:25940:27620:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      6.202
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.069

    - Propagation time:                      7.164
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.095

    Number of logic level(s):                4
    Starting point:                          u_ao_mem_ctrl.capture_mem_addr[6] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top|clk_i [rising] on pin CLK

Instance / Net                                               Pin      Pin               Arrival     No. of    
Name                                           Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_addr[6]              DFFCE         Q        Out     0.367     0.367       -         
capture_mem_addr[6]                            Net           -        -       1.021     -           3         
u_ao_mem_ctrl.un1_capture_mem_addr_7_N_2L1     LUT3          I1       In      -         1.388       -         
u_ao_mem_ctrl.un1_capture_mem_addr_7_N_2L1     LUT3          F        Out     1.099     2.487       -         
un1_capture_mem_addr_7_N_2L1                   Net           -        -       0.766     -           1         
u_ao_mem_ctrl.un1_capture_mem_addr_7           LUT4          I3       In      -         3.253       -         
u_ao_mem_ctrl.un1_capture_mem_addr_7           LUT4          F        Out     0.626     3.879       -         
N_14_i_1                                       Net           -        -       1.082     -           13        
u_ao_mem_ctrl.un1_start_reg_0_mb_mb_RNO        LUT4          I0       In      -         4.961       -         
u_ao_mem_ctrl.un1_start_reg_0_mb_mb_RNO        LUT4          F        Out     1.032     5.993       -         
un1_start_reg_0_mb_mb_0                        Net           -        -       0.000     -           1         
u_ao_mem_ctrl.un1_start_reg_0_mb_mb            MUX2_LUT5     I0       In      -         5.993       -         
u_ao_mem_ctrl.un1_start_reg_0_mb_mb            MUX2_LUT5     O        Out     0.150     6.143       -         
un1_start_reg_0_mb_mb                          Net           -        -       1.021     -           1         
u_ao_mem_ctrl.capture_mem_wr                   DFFCE         CE       In      -         7.164       -         
==============================================================================================================
Total path delay (propagation time + setup) of 7.297 is 3.407(46.7%) logic and 3.890(53.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      6.202
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.069

    - Propagation time:                      7.164
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.095

    Number of logic level(s):                4
    Starting point:                          u_ao_mem_ctrl.capture_mem_addr[6] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top|clk_i [rising] on pin CLK

Instance / Net                                               Pin      Pin               Arrival     No. of    
Name                                           Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_addr[6]              DFFCE         Q        Out     0.367     0.367       -         
capture_mem_addr[6]                            Net           -        -       1.021     -           3         
u_ao_mem_ctrl.un1_capture_mem_addr_7_N_2L1     LUT3          I1       In      -         1.388       -         
u_ao_mem_ctrl.un1_capture_mem_addr_7_N_2L1     LUT3          F        Out     1.099     2.487       -         
un1_capture_mem_addr_7_N_2L1                   Net           -        -       0.766     -           1         
u_ao_mem_ctrl.un1_capture_mem_addr_7           LUT4          I3       In      -         3.253       -         
u_ao_mem_ctrl.un1_capture_mem_addr_7           LUT4          F        Out     0.626     3.879       -         
N_14_i_1                                       Net           -        -       1.082     -           13        
u_ao_mem_ctrl.un1_start_reg_0_mb_mb_RNO_0      LUT4          I0       In      -         4.961       -         
u_ao_mem_ctrl.un1_start_reg_0_mb_mb_RNO_0      LUT4          F        Out     1.032     5.993       -         
un1_start_reg_0_mb_mb_1                        Net           -        -       0.000     -           1         
u_ao_mem_ctrl.un1_start_reg_0_mb_mb            MUX2_LUT5     I1       In      -         5.993       -         
u_ao_mem_ctrl.un1_start_reg_0_mb_mb            MUX2_LUT5     O        Out     0.150     6.143       -         
un1_start_reg_0_mb_mb                          Net           -        -       1.021     -           1         
u_ao_mem_ctrl.capture_mem_wr                   DFFCE         CE       In      -         7.164       -         
==============================================================================================================
Total path delay (propagation time + setup) of 7.297 is 3.407(46.7%) logic and 3.890(53.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      6.202
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.069

    - Propagation time:                      7.096
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.027

    Number of logic level(s):                4
    Starting point:                          u_ao_mem_ctrl.capture_mem_addr[3] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top|clk_i [rising] on pin CLK

Instance / Net                                               Pin      Pin               Arrival     No. of    
Name                                           Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_addr[3]              DFFCE         Q        Out     0.367     0.367       -         
capture_mem_addr[3]                            Net           -        -       1.021     -           3         
u_ao_mem_ctrl.un1_capture_mem_addr_7_N_2L1     LUT3          I0       In      -         1.388       -         
u_ao_mem_ctrl.un1_capture_mem_addr_7_N_2L1     LUT3          F        Out     1.032     2.420       -         
un1_capture_mem_addr_7_N_2L1                   Net           -        -       0.766     -           1         
u_ao_mem_ctrl.un1_capture_mem_addr_7           LUT4          I3       In      -         3.186       -         
u_ao_mem_ctrl.un1_capture_mem_addr_7           LUT4          F        Out     0.626     3.812       -         
N_14_i_1                                       Net           -        -       1.082     -           13        
u_ao_mem_ctrl.un1_start_reg_0_mb_mb_RNO        LUT4          I0       In      -         4.894       -         
u_ao_mem_ctrl.un1_start_reg_0_mb_mb_RNO        LUT4          F        Out     1.032     5.926       -         
un1_start_reg_0_mb_mb_0                        Net           -        -       0.000     -           1         
u_ao_mem_ctrl.un1_start_reg_0_mb_mb            MUX2_LUT5     I0       In      -         5.926       -         
u_ao_mem_ctrl.un1_start_reg_0_mb_mb            MUX2_LUT5     O        Out     0.150     6.075       -         
un1_start_reg_0_mb_mb                          Net           -        -       1.021     -           1         
u_ao_mem_ctrl.capture_mem_wr                   DFFCE         CE       In      -         7.096       -         
==============================================================================================================
Total path delay (propagation time + setup) of 7.229 is 3.340(46.2%) logic and 3.890(53.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      6.202
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.069

    - Propagation time:                      7.096
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.027

    Number of logic level(s):                4
    Starting point:                          u_ao_mem_ctrl.capture_mem_addr[3] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top|clk_i [rising] on pin CLK

Instance / Net                                               Pin      Pin               Arrival     No. of    
Name                                           Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_addr[3]              DFFCE         Q        Out     0.367     0.367       -         
capture_mem_addr[3]                            Net           -        -       1.021     -           3         
u_ao_mem_ctrl.un1_capture_mem_addr_7_N_2L1     LUT3          I0       In      -         1.388       -         
u_ao_mem_ctrl.un1_capture_mem_addr_7_N_2L1     LUT3          F        Out     1.032     2.420       -         
un1_capture_mem_addr_7_N_2L1                   Net           -        -       0.766     -           1         
u_ao_mem_ctrl.un1_capture_mem_addr_7           LUT4          I3       In      -         3.186       -         
u_ao_mem_ctrl.un1_capture_mem_addr_7           LUT4          F        Out     0.626     3.812       -         
N_14_i_1                                       Net           -        -       1.082     -           13        
u_ao_mem_ctrl.un1_start_reg_0_mb_mb_RNO_0      LUT4          I0       In      -         4.894       -         
u_ao_mem_ctrl.un1_start_reg_0_mb_mb_RNO_0      LUT4          F        Out     1.032     5.926       -         
un1_start_reg_0_mb_mb_1                        Net           -        -       0.000     -           1         
u_ao_mem_ctrl.un1_start_reg_0_mb_mb            MUX2_LUT5     I1       In      -         5.926       -         
u_ao_mem_ctrl.un1_start_reg_0_mb_mb            MUX2_LUT5     O        Out     0.150     6.075       -         
un1_start_reg_0_mb_mb                          Net           -        -       1.021     -           1         
u_ao_mem_ctrl.capture_mem_wr                   DFFCE         CE       In      -         7.096       -         
==============================================================================================================
Total path delay (propagation time + setup) of 7.229 is 3.340(46.2%) logic and 3.890(53.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      6.202
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.069

    - Propagation time:                      6.887
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.817

    Number of logic level(s):                4
    Starting point:                          u_ao_mem_ctrl.capture_mem_addr[7] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top|clk_i [rising] on pin CLK

Instance / Net                                               Pin      Pin               Arrival     No. of    
Name                                           Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_addr[7]              DFFCE         Q        Out     0.367     0.367       -         
capture_mem_addr[7]                            Net           -        -       1.021     -           3         
u_ao_mem_ctrl.un1_capture_mem_addr_7_N_2L1     LUT3          I2       In      -         1.388       -         
u_ao_mem_ctrl.un1_capture_mem_addr_7_N_2L1     LUT3          F        Out     0.822     2.210       -         
un1_capture_mem_addr_7_N_2L1                   Net           -        -       0.766     -           1         
u_ao_mem_ctrl.un1_capture_mem_addr_7           LUT4          I3       In      -         2.976       -         
u_ao_mem_ctrl.un1_capture_mem_addr_7           LUT4          F        Out     0.626     3.602       -         
N_14_i_1                                       Net           -        -       1.082     -           13        
u_ao_mem_ctrl.un1_start_reg_0_mb_mb_RNO        LUT4          I0       In      -         4.684       -         
u_ao_mem_ctrl.un1_start_reg_0_mb_mb_RNO        LUT4          F        Out     1.032     5.716       -         
un1_start_reg_0_mb_mb_0                        Net           -        -       0.000     -           1         
u_ao_mem_ctrl.un1_start_reg_0_mb_mb            MUX2_LUT5     I0       In      -         5.716       -         
u_ao_mem_ctrl.un1_start_reg_0_mb_mb            MUX2_LUT5     O        Out     0.150     5.866       -         
un1_start_reg_0_mb_mb                          Net           -        -       1.021     -           1         
u_ao_mem_ctrl.capture_mem_wr                   DFFCE         CE       In      -         6.887       -         
==============================================================================================================
Total path delay (propagation time + setup) of 7.020 is 3.130(44.6%) logic and 3.890(55.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
<a name=clockReport18></a>Detailed Report for Clock: ao_top|control[0]</a>
====================================



<a name=startingSlack19></a>Starting Points with Worst Slack</a>
********************************

                                Starting                                                                Arrival           
Instance                        Reference             Type      Pin     Net                             Time        Slack 
                                Clock                                                                                     
--------------------------------------------------------------------------------------------------------------------------
word_count[0]                   ao_top|control[0]     DFFCE     Q       word_count[0]                   0.367       -1.494
word_count[1]                   ao_top|control[0]     DFFCE     Q       word_count[1]                   0.367       -1.437
word_count[2]                   ao_top|control[0]     DFFCE     Q       word_count[2]                   0.367       -1.380
internal_register_select[3]     ao_top|control[0]     DFFCE     Q       internal_register_select[3]     0.367       -1.236
internal_register_select[2]     ao_top|control[0]     DFFCE     Q       internal_register_select[2]     0.367       -1.169
internal_register_select[7]     ao_top|control[0]     DFFCE     Q       internal_register_select[7]     0.367       -1.169
data_register[22]               ao_top|control[0]     DFFCE     Q       data_register[22]               0.367       -1.151
word_count[3]                   ao_top|control[0]     DFFCE     Q       word_count[3]                   0.367       -1.103
internal_register_select[6]     ao_top|control[0]     DFFCE     Q       internal_register_select[6]     0.367       -1.101
bit_count[1]                    ao_top|control[0]     DFFC      Q       bit_count[1]                    0.367       -1.019
==========================================================================================================================


<a name=endingSlack20></a>Ending Points with Worst Slack</a>
******************************

                       Starting                                           Required           
Instance               Reference             Type      Pin     Net        Time         Slack 
                       Clock                                                                 
---------------------------------------------------------------------------------------------
address_counter[0]     ao_top|control[0]     DFFCE     CE      N_23_i     8.332        -1.494
address_counter[1]     ao_top|control[0]     DFFCE     CE      N_23_i     8.332        -1.494
address_counter[2]     ao_top|control[0]     DFFCE     CE      N_23_i     8.332        -1.494
address_counter[3]     ao_top|control[0]     DFFCE     CE      N_23_i     8.332        -1.494
address_counter[4]     ao_top|control[0]     DFFCE     CE      N_23_i     8.332        -1.494
address_counter[5]     ao_top|control[0]     DFFCE     CE      N_23_i     8.332        -1.494
address_counter[6]     ao_top|control[0]     DFFCE     CE      N_23_i     8.332        -1.494
address_counter[7]     ao_top|control[0]     DFFCE     CE      N_23_i     8.332        -1.494
address_counter[8]     ao_top|control[0]     DFFCE     CE      N_23_i     8.332        -1.494
address_counter[9]     ao_top|control[0]     DFFCE     CE      N_23_i     8.332        -1.494
=============================================================================================



<a name=worstPaths21></a>Worst Path Information</a>
<a href="C:\Gowin\gowin-blink\impl\temp\gao\ao_0\rev_1\ao_0.srr:srsfC:\Gowin\gowin-blink\impl\temp\gao\ao_0\rev_1\ao_0.srs:fp:45265:47785:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      8.465
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.332

    - Propagation time:                      9.826
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.494

    Number of logic level(s):                7
    Starting point:                          word_count[0] / Q
    Ending point:                            address_counter[0] / CE
    The start point is clocked by            ao_top|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top|control[0] [rising] on pin CLK

Instance / Net                                        Pin      Pin               Arrival     No. of    
Name                                        Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
word_count[0]                               DFFCE     Q        Out     0.367     0.367       -         
word_count[0]                               Net       -        -       1.021     -           3         
decremented_word_count_cry_0_0              ALU       I0       In      -         1.388       -         
decremented_word_count_cry_0_0              ALU       COUT     Out     0.958     2.346       -         
decremented_word_count_cry_0                Net       -        -       0.000     -           1         
decremented_word_count_cry_1_0              ALU       CIN      In      -         2.346       -         
decremented_word_count_cry_1_0              ALU       COUT     Out     0.057     2.403       -         
decremented_word_count_cry_1                Net       -        -       0.000     -           1         
decremented_word_count_cry_2_0              ALU       CIN      In      -         2.403       -         
decremented_word_count_cry_2_0              ALU       COUT     Out     0.057     2.460       -         
decremented_word_count_cry_2                Net       -        -       0.000     -           1         
decremented_word_count_cry_3_0              ALU       CIN      In      -         2.460       -         
decremented_word_count_cry_3_0              ALU       SUM      Out     0.563     3.023       -         
decremented_word_count[3]                   Net       -        -       1.021     -           2         
decremented_word_count_cry_2_0_RNI6U0R1     LUT4      I1       In      -         4.044       -         
decremented_word_count_cry_2_0_RNI6U0R1     LUT4      F        Out     1.099     5.143       -         
decremented_word_count_cry_2_0_RNI6U0R1     Net       -        -       0.766     -           1         
decremented_word_count_s_15_0_RNIMV629      LUT4      I1       In      -         5.909       -         
decremented_word_count_s_15_0_RNIMV629      LUT4      F        Out     1.099     7.008       -         
N_23_i_1                                    Net       -        -       0.766     -           1         
decremented_word_count_s_15_0_RNI1605I      LUT4      I0       In      -         7.773       -         
decremented_word_count_s_15_0_RNI1605I      LUT4      F        Out     1.032     8.805       -         
N_23_i                                      Net       -        -       1.021     -           10        
address_counter[0]                          DFFCE     CE       In      -         9.826       -         
=======================================================================================================
Total path delay (propagation time + setup) of 9.959 is 5.365(53.9%) logic and 4.594(46.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      8.465
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.332

    - Propagation time:                      9.826
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.494

    Number of logic level(s):                7
    Starting point:                          word_count[0] / Q
    Ending point:                            address_counter[1] / CE
    The start point is clocked by            ao_top|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top|control[0] [rising] on pin CLK

Instance / Net                                        Pin      Pin               Arrival     No. of    
Name                                        Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
word_count[0]                               DFFCE     Q        Out     0.367     0.367       -         
word_count[0]                               Net       -        -       1.021     -           3         
decremented_word_count_cry_0_0              ALU       I0       In      -         1.388       -         
decremented_word_count_cry_0_0              ALU       COUT     Out     0.958     2.346       -         
decremented_word_count_cry_0                Net       -        -       0.000     -           1         
decremented_word_count_cry_1_0              ALU       CIN      In      -         2.346       -         
decremented_word_count_cry_1_0              ALU       COUT     Out     0.057     2.403       -         
decremented_word_count_cry_1                Net       -        -       0.000     -           1         
decremented_word_count_cry_2_0              ALU       CIN      In      -         2.403       -         
decremented_word_count_cry_2_0              ALU       COUT     Out     0.057     2.460       -         
decremented_word_count_cry_2                Net       -        -       0.000     -           1         
decremented_word_count_cry_3_0              ALU       CIN      In      -         2.460       -         
decremented_word_count_cry_3_0              ALU       SUM      Out     0.563     3.023       -         
decremented_word_count[3]                   Net       -        -       1.021     -           2         
decremented_word_count_cry_2_0_RNI6U0R1     LUT4      I1       In      -         4.044       -         
decremented_word_count_cry_2_0_RNI6U0R1     LUT4      F        Out     1.099     5.143       -         
decremented_word_count_cry_2_0_RNI6U0R1     Net       -        -       0.766     -           1         
decremented_word_count_s_15_0_RNIMV629      LUT4      I1       In      -         5.909       -         
decremented_word_count_s_15_0_RNIMV629      LUT4      F        Out     1.099     7.008       -         
N_23_i_1                                    Net       -        -       0.766     -           1         
decremented_word_count_s_15_0_RNI1605I      LUT4      I0       In      -         7.773       -         
decremented_word_count_s_15_0_RNI1605I      LUT4      F        Out     1.032     8.805       -         
N_23_i                                      Net       -        -       1.021     -           10        
address_counter[1]                          DFFCE     CE       In      -         9.826       -         
=======================================================================================================
Total path delay (propagation time + setup) of 9.959 is 5.365(53.9%) logic and 4.594(46.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      8.465
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.332

    - Propagation time:                      9.826
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.494

    Number of logic level(s):                7
    Starting point:                          word_count[0] / Q
    Ending point:                            address_counter[2] / CE
    The start point is clocked by            ao_top|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top|control[0] [rising] on pin CLK

Instance / Net                                        Pin      Pin               Arrival     No. of    
Name                                        Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
word_count[0]                               DFFCE     Q        Out     0.367     0.367       -         
word_count[0]                               Net       -        -       1.021     -           3         
decremented_word_count_cry_0_0              ALU       I0       In      -         1.388       -         
decremented_word_count_cry_0_0              ALU       COUT     Out     0.958     2.346       -         
decremented_word_count_cry_0                Net       -        -       0.000     -           1         
decremented_word_count_cry_1_0              ALU       CIN      In      -         2.346       -         
decremented_word_count_cry_1_0              ALU       COUT     Out     0.057     2.403       -         
decremented_word_count_cry_1                Net       -        -       0.000     -           1         
decremented_word_count_cry_2_0              ALU       CIN      In      -         2.403       -         
decremented_word_count_cry_2_0              ALU       COUT     Out     0.057     2.460       -         
decremented_word_count_cry_2                Net       -        -       0.000     -           1         
decremented_word_count_cry_3_0              ALU       CIN      In      -         2.460       -         
decremented_word_count_cry_3_0              ALU       SUM      Out     0.563     3.023       -         
decremented_word_count[3]                   Net       -        -       1.021     -           2         
decremented_word_count_cry_2_0_RNI6U0R1     LUT4      I1       In      -         4.044       -         
decremented_word_count_cry_2_0_RNI6U0R1     LUT4      F        Out     1.099     5.143       -         
decremented_word_count_cry_2_0_RNI6U0R1     Net       -        -       0.766     -           1         
decremented_word_count_s_15_0_RNIMV629      LUT4      I1       In      -         5.909       -         
decremented_word_count_s_15_0_RNIMV629      LUT4      F        Out     1.099     7.008       -         
N_23_i_1                                    Net       -        -       0.766     -           1         
decremented_word_count_s_15_0_RNI1605I      LUT4      I0       In      -         7.773       -         
decremented_word_count_s_15_0_RNI1605I      LUT4      F        Out     1.032     8.805       -         
N_23_i                                      Net       -        -       1.021     -           10        
address_counter[2]                          DFFCE     CE       In      -         9.826       -         
=======================================================================================================
Total path delay (propagation time + setup) of 9.959 is 5.365(53.9%) logic and 4.594(46.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      8.465
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.332

    - Propagation time:                      9.826
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.494

    Number of logic level(s):                7
    Starting point:                          word_count[0] / Q
    Ending point:                            address_counter[3] / CE
    The start point is clocked by            ao_top|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top|control[0] [rising] on pin CLK

Instance / Net                                        Pin      Pin               Arrival     No. of    
Name                                        Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
word_count[0]                               DFFCE     Q        Out     0.367     0.367       -         
word_count[0]                               Net       -        -       1.021     -           3         
decremented_word_count_cry_0_0              ALU       I0       In      -         1.388       -         
decremented_word_count_cry_0_0              ALU       COUT     Out     0.958     2.346       -         
decremented_word_count_cry_0                Net       -        -       0.000     -           1         
decremented_word_count_cry_1_0              ALU       CIN      In      -         2.346       -         
decremented_word_count_cry_1_0              ALU       COUT     Out     0.057     2.403       -         
decremented_word_count_cry_1                Net       -        -       0.000     -           1         
decremented_word_count_cry_2_0              ALU       CIN      In      -         2.403       -         
decremented_word_count_cry_2_0              ALU       COUT     Out     0.057     2.460       -         
decremented_word_count_cry_2                Net       -        -       0.000     -           1         
decremented_word_count_cry_3_0              ALU       CIN      In      -         2.460       -         
decremented_word_count_cry_3_0              ALU       SUM      Out     0.563     3.023       -         
decremented_word_count[3]                   Net       -        -       1.021     -           2         
decremented_word_count_cry_2_0_RNI6U0R1     LUT4      I1       In      -         4.044       -         
decremented_word_count_cry_2_0_RNI6U0R1     LUT4      F        Out     1.099     5.143       -         
decremented_word_count_cry_2_0_RNI6U0R1     Net       -        -       0.766     -           1         
decremented_word_count_s_15_0_RNIMV629      LUT4      I1       In      -         5.909       -         
decremented_word_count_s_15_0_RNIMV629      LUT4      F        Out     1.099     7.008       -         
N_23_i_1                                    Net       -        -       0.766     -           1         
decremented_word_count_s_15_0_RNI1605I      LUT4      I0       In      -         7.773       -         
decremented_word_count_s_15_0_RNI1605I      LUT4      F        Out     1.032     8.805       -         
N_23_i                                      Net       -        -       1.021     -           10        
address_counter[3]                          DFFCE     CE       In      -         9.826       -         
=======================================================================================================
Total path delay (propagation time + setup) of 9.959 is 5.365(53.9%) logic and 4.594(46.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      8.465
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.332

    - Propagation time:                      9.826
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.494

    Number of logic level(s):                7
    Starting point:                          word_count[0] / Q
    Ending point:                            address_counter[4] / CE
    The start point is clocked by            ao_top|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top|control[0] [rising] on pin CLK

Instance / Net                                        Pin      Pin               Arrival     No. of    
Name                                        Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
word_count[0]                               DFFCE     Q        Out     0.367     0.367       -         
word_count[0]                               Net       -        -       1.021     -           3         
decremented_word_count_cry_0_0              ALU       I0       In      -         1.388       -         
decremented_word_count_cry_0_0              ALU       COUT     Out     0.958     2.346       -         
decremented_word_count_cry_0                Net       -        -       0.000     -           1         
decremented_word_count_cry_1_0              ALU       CIN      In      -         2.346       -         
decremented_word_count_cry_1_0              ALU       COUT     Out     0.057     2.403       -         
decremented_word_count_cry_1                Net       -        -       0.000     -           1         
decremented_word_count_cry_2_0              ALU       CIN      In      -         2.403       -         
decremented_word_count_cry_2_0              ALU       COUT     Out     0.057     2.460       -         
decremented_word_count_cry_2                Net       -        -       0.000     -           1         
decremented_word_count_cry_3_0              ALU       CIN      In      -         2.460       -         
decremented_word_count_cry_3_0              ALU       SUM      Out     0.563     3.023       -         
decremented_word_count[3]                   Net       -        -       1.021     -           2         
decremented_word_count_cry_2_0_RNI6U0R1     LUT4      I1       In      -         4.044       -         
decremented_word_count_cry_2_0_RNI6U0R1     LUT4      F        Out     1.099     5.143       -         
decremented_word_count_cry_2_0_RNI6U0R1     Net       -        -       0.766     -           1         
decremented_word_count_s_15_0_RNIMV629      LUT4      I1       In      -         5.909       -         
decremented_word_count_s_15_0_RNIMV629      LUT4      F        Out     1.099     7.008       -         
N_23_i_1                                    Net       -        -       0.766     -           1         
decremented_word_count_s_15_0_RNI1605I      LUT4      I0       In      -         7.773       -         
decremented_word_count_s_15_0_RNI1605I      LUT4      F        Out     1.032     8.805       -         
N_23_i                                      Net       -        -       1.021     -           10        
address_counter[4]                          DFFCE     CE       In      -         9.826       -         
=======================================================================================================
Total path delay (propagation time + setup) of 9.959 is 5.365(53.9%) logic and 4.594(46.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
<a name=clockReport22></a>Detailed Report for Clock: System</a>
====================================



<a name=startingSlack23></a>Starting Points with Worst Slack</a>
********************************

                                         Starting                                           Arrival          
Instance                                 Reference     Type     Pin     Net                 Time        Slack
                                         Clock                                                               
-------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     System        INV      O       capture_end         0.000       4.016
address_counter_cry_0_RNO[0]             System        INV      O       address_counter     0.000       5.214
=============================================================================================================


<a name=endingSlack24></a>Ending Points with Worst Slack</a>
******************************

                              Starting                                                          Required          
Instance                      Reference     Type      Pin     Net                               Time         Slack
                              Clock                                                                               
------------------------------------------------------------------------------------------------------------------
capture_start_sel             System        DFFCE     CE      internal_reg_start_dly_2_i[0]     6.069        4.016
internal_reg_start_dly[0]     System        DFFC      D       internal_reg_start_dly_2[0]       6.069        4.016
capture_end_dly               System        DFFP      D       capture_end                       6.069        5.048
address_counter[9]            System        DFFCE     D       address_counter_s[9]              8.332        5.214
address_counter[8]            System        DFFCE     D       address_counter_s[8]              8.332        5.271
address_counter[7]            System        DFFCE     D       address_counter_s[7]              8.332        5.328
address_counter[6]            System        DFFCE     D       address_counter_s[6]              8.332        5.385
address_counter[5]            System        DFFCE     D       address_counter_s[5]              8.332        5.442
address_counter[4]            System        DFFCE     D       address_counter_s[4]              8.332        5.499
address_counter[3]            System        DFFCE     D       address_counter_s[3]              8.332        5.556
==================================================================================================================



<a name=worstPaths25></a>Worst Path Information</a>
<a href="C:\Gowin\gowin-blink\impl\temp\gao\ao_0\rev_1\ao_0.srr:srsfC:\Gowin\gowin-blink\impl\temp\gao\ao_0\rev_1\ao_0.srs:fp:67850:68462:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      6.202
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.069

    - Propagation time:                      2.053
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 4.016

    Number of logic level(s):                1
    Starting point:                          u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 / O
    Ending point:                            capture_start_sel / CE
    The start point is clocked by            System [rising]
    The end   point is clocked by            ao_top|clk_i [rising] on pin CLK

Instance / Net                                     Pin      Pin               Arrival     No. of    
Name                                     Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     INV       O        Out     0.000     0.000       -         
capture_end                              Net       -        -       1.021     -           4         
capture_start_sel_RNO                    LUT3      I0       In      -         1.021       -         
capture_start_sel_RNO                    LUT3      F        Out     1.032     2.053       -         
internal_reg_start_dly_2_i[0]            Net       -        -       0.000     -           1         
capture_start_sel                        DFFCE     CE       In      -         2.053       -         
====================================================================================================
Total path delay (propagation time + setup) of 2.186 is 1.165(53.3%) logic and 1.021(46.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 193MB peak: 195MB)


Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 193MB peak: 195MB)

---------------------------------------
<a name=resourceUsage26></a>Resource Usage Report for ao_top </a>

Mapping to part: gw1n_4lqfp144-6
Cell usage:
ALU             36 uses
DFFC            15 uses
DFFCE           95 uses
DFFNP           2 uses
DFFP            2 uses
GSR             1 use
INV             2 uses
MUX2_LUT5       18 uses
MUX2_LUT6       7 uses
SDP             1 use
LUT2            29 uses
LUT3            24 uses
LUT4            92 uses

I/O ports: 16
I/O primitives: 16
IBUF           14 uses
OBUF           2 uses

I/O Register bits:                  0
Register bits not including I/Os:   114 of 3456 (3%)

RAM/ROM usage summary
Block Rams : 1 of 10 (10%)

Total load per clock:
   ao_top|clk_i: 1
   ao_top|control[0]: 93

@S |Mapping Summary:
Total  LUTs: 145 (3%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 40MB peak: 195MB)

Process took 0h:00m:05s realtime, 0h:00m:04s cputime
# Mon Oct  8 09:41:50 2018

###########################################################]

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